Illustrative and Complementary Information On
 The Algebra Of Priority (AOP )
By
Abu-Msameh, Ramadan K. 
JAN 10, 2001
Comments On Prioritors Use
In Sequential Circuit Design 
"The development of AOP was originated strictly for the purpose of describing and analyzing digital systems design"

This section is from a paper on the applications of AOP in sequential circuits design. This section is not intended to give full details but rather shows some of the insights of AOP and its applications at the hardware level.  

READING AOP DIGITAL CIRCUITS

A circled number with an arrow, , pointing to a point in the circuit indicates the minimum radix system that can be used at this point.  For example, a circled 4 in the circuit means that this point operate with a system with a minimum radix of '4' or higher and can not operate in the ternary or binary systems since their radices are less than the minimum radix.

A number inside a rectangle represents a source for a constant digit and a rectangle with an arrow pointing up represents a source for the circuit supremum-state and a rectangle with an arrow pointing down represents a source for the circuit infimum-state.

The term hard radix and soft radix are commonly used by AOP. The radix used to implement the hardware of a digital circuit is called the hard-radix and  any radix less than the hard-radix is called a soft-radix.  For example, a quaternary digital counter can count in the quaternary, ternary and binary systems.  Thus the ternary and binary systems are called soft radices relative to the quaternary system.

At the hardware level, conservative unary operators of AOP are called in converters and inverters. Inverters are self-inverse conservative operators and we use the following symbol to refer to them in AOP circuits.  On the other hand, converters are none self-inverse conservative unary operators and we use the following symbol to refer to them in AOP circuits.  Inverters are always indicated by a circle and converters by a square.

AOP orthogonal operators use the following symbol .  A three-digit number indicates the function code of the operator but one digit indicates the activating state and by default its active state is equal to system supremum-state and inactive state is equal to system infimum-state.

AOP Design Rules:

  1.  Inverters in AOP are analogous to the NOT inverter in the binary system for any STAS system and it is obtained by applying the costar operation on one of the STAS system prioritors.

  2.  All control signals are active if they are in the supremum-state and inactive if they are in the infimum-state.

  3.  The CLR control signal means setting the output-state to the supremum-state.

  4.  The SET control signal means setting the output-state to the infimum-state.

  5.  Level-clocked devices store data at the cell infimum-state and block data at the cell supremum-state

  6.  Edge-triggered devices store data at the clock transition from the cell supremum-state to the cell infimum-state.

  7.  In all digital circuits, an unspecified unary conservative operator is assumed to be, by default, the unary operator obtained by taking the costar operation of one of the prioritors of the STAS system in use.

CONTROLLED PRIORITY LATCH CELL (CPL)

The controlled priority latch uses a simple priority storage cell with three control signals and additional two prioritors, three unary conservative operators and two unary orthogonal operators. It is shown bellow. The control signals are: ENABLE, ISC, SET and CLR (clear) signals. The analysis of this circuit shows that if ENABLE =a^{¾  Ú} (infimum of a) then, the circuit keeps its old data and if ENABLE =a^{¾ Ú}, the circuit stores the data at the input terminal.

In the controlled priority latch cell, the data present at the D input will be stored when the ENABLE signal switches from the cell supremum-state to the cell infimum-state and the Q1 terminal goes to the same data at the D-input. Thus, the output keeps following the input data until the ENABLE signal switches to the cell supremum-state and at this point the cell keeps the last input data stored.

Analysis by AOP

The ISC (Idle/Set/Clear) control signal has three states and is used to setup or initialize the priority storage cell to a defined state. For example, when the power is applied to the priority storage cell, it is not possible to predict the starting output-state of the cell. Therefore, if the cell has to start off in a particular state to ensure the proper operation of its circuit, then it has to be placed in that particular state by applying the proper signal on the ISC.  The ISC is fed to two unary orthogonal operators: y=DSa^{¾ Ú}a¾L and g=DCa^{¾ Ú}a¾L. When the ISC=S then the ‘y’ orthogonal operator switches to the supremum-state of a causing a SET to the Q output and at the same time the ‘g’ unary orthogonal operator does not change its state and remains at its infimum-state.  Also, when the ISC=C then the ‘g’ unary orthogonal operator switches to the cell supremum-state of a causing a CLR to the Q output and at the same time the ‘y’ unary orthogonal operator does not change its state and remains at the cell infimum-state.  When the ICS=I, then the two unary orthogonal operators do not change their states and stay at the cell infimum-state which does not affect the data stored in the storage cell.  The ‘I’, ‘S’ and ‘C’ signals are distinct and none of them are equal.  The number of ways to select values to these signals is given by z!/(z-3)!.  The number of ways is 24 in the quaternary system, 6 in the ternary system and none in the binary system.   The binary system has none because it does not have three distinct digits to represent the ‘I’, ‘S’, and ‘C’.  Therefore, in the binary system the ‘SET’ and ‘CLR’ terminals must do the control part independently with no unary orthogonal operators.  One problem will occur in the binary system in this if both the SET and CLR are set to the cell supremum-state.  This problem is avoided for systems of radices more than two. The values for 'C' and 'S' are evaluated by 
C=ISC^{¾  DCa¾ Úa¾ Ù}  and S=ISC^{¾ DSa¾ Úa¾ Ù}.

Table-3 shows the function of the priority controlled latch cell.  The symbols used in the table are explained in Table-4.  From the table, entry- 1 shows that when the ENABLE signal is at the cell supremum-state and the cell keeps its stored data;  entry-2 shows that when the ENABLE switches to the cell infimum-state, the cell stores data at the input.  The table shows the cell can store or keep its data only when the ISC is idle.  Also,  when the ISC is at the SET state, the Q output of the cell switches to the cell infimum-state and the Q¾ output switches to the cell supremum-state and when the ISC is at the CLR state, the Q output of the cell switches to the cell supremum-state and the Q¾ output switches to the cell infimum-state.

Design Example-3: On Controlled Priority Latch Cell.  In the quaternary system, let the prioritor a=Q5=4S0312 be used in a priority storage cell.  From Table-1, f=a#=4S1032. This cell has the ‘0’ as its supremum-state and the ‘2’ as its infimum-state.  Assuming ‘0’ is the idle signal, ‘1’ is the SET signal and ‘2’ is the CLR signal then the ‘y’ and ‘g’ unary orthogonal operator become y=D120 and g=D220. In the ternary system, let the prioritor a=T5=3S201 be used in a priority storage cell.  From Table-1, f=a#=3S120. This cell has the ‘2’ as its supremum-state and the ‘1’ as its infimum-state.  Assuming ‘2’ is the idle signal, ‘0’ is the SET signal and ‘1’ is the CLR signal then the ‘y’ and ‘g’ unary orthogonal operator become y=D012 and g=D112.  In the binary system, let the prioritor a=B1=2S01 be used in a priority storage cell.  From Table-1, f=a#=2S01. This cell has the ‘0’ as its supremum-state and the ‘1’ as its infimum-state.  No unary orthogonal operator is needed. The ‘SET’ and ‘CLR’ terminals must do the control part independently.  

7- INSTANTANEOUS PRIORITY REGISTER CELL (IPR)

            Figure-16 shows the instantaneous priority register cell.  The cell has three priority storage cells.  The left side has two priority storage cells and the right side has one priority storage cell.  The upper cell in the left side is used to store the costar-image of the input data  and the lower cell is used to store the data itself.   The upper and lower cells, called primary cells or temporary storage cells, together form a data-lock circuit (DLC). They store data instantaneously at the clock transition from the cell supremum-state to the cell infimum-state and after then they lock the data path immediately following the clock transition.  And any change in the input data while the clock is in the cell infimum-state will never be stored by the primary cells.  The two cells will store data temporarily during the clock infimum-time duration and they lose their data when the clock switches back to the cell supremum-state.  In order to store data permanently we added the third priority storage  cell which is called the secondary cell or permanent storage cell. This cell stores the temporarily loaded data from the secondary cells while the clock is in the cell infimum-state.  When the clock switches to the cell supremum-state, the data is lost in the temporary storage cells but kept in the permanent storage cell.  Thus, the IPR cell, unlike the PR cell, is an edge-triggered cell at the clock transition from the cell supremum-state to the cell infimum-state.

The IPR cell Analysis by AOP

 The IPR cell has three phases of operations.  The first is when the clock is at the cell supremum-state, the second is when the clock switches from the cell supremum-state to the cell infimum-state and the third when the clock remains in the cell infimum-state.

 In the first phase, when the clock is at the cell supremum-state, its supremacy dominate all other inputs in the second and third prioritors and the followings occur:  (1)  The AQ2 and BQ1 outputs are switched to the cell infimum-state and have the lowest priority in the cell structure.  This make the CQ2 dominate the CD1 input and CQ1 dominate the CD2 input and hence the C-cell keeps holding on its previously stored data.  (2) The infimum signal of the BQ1 opens the fourth prioritor causing the DATA to flow through the fourth costar unary operator which passes the costar image of the data to the third prioritor.  The imaged-data is blocked to pass through the third prioritor by the supremum signal of the clock.  (3) The infimum signal of the AQ2 opens the first prioritor causing the data[1]  costar image  to flow through the first costar unary operator.  This costar unary operator converts that data image to its original data and passes it to the second prioritor. The data is blocked to pass through the second prioritor by the supremum signal of the clock.  At this stage the data and its image are blocked to pass through the channels of the A and B primary cells.

 In the second phase, when the clock switches from the cell supremum-state to the cell infimum-state the followings occur:  (1) The signal opens the second and third prioritors and passes the blocked data-image and the blocked data through the second and third prioritors. The A and B primary cells act as a normal priority storage cells and store the input data. The 'A' primary cell feeds the data image (D^¾) to the CD1 input of the secondary cell and the 'B' cell feeds the data to the CD2 input of the secondary cell.  The secondary cell instantaneously stores the same data.  At this point in time all the three cells are storing the same data.

 In the third phase, the 'A' and 'B' primary cells block any change to the data to reach the secondary cell when the clock remains at the cell infimum-state.  This blocking property can occur if the two followings conditions are satisfied: (1) If the priority of the new data is less than the priority of the BQ1, then the new data is blocked by the priority principle. (2) If the priority of the new data is greater than the priority of the BQ1, then the priority of the AQ2 must be grater than the priority of the data image to prevent the new data to enter the 'A' primary cell. The first condition is easy to understand because when the priority of the new data is less than the priority of the BQ1 at the fourth prioritor, then by the priority principle the fourth prioritor will block the new data and passes the data at the BQ1.  However, in the second condition, we have to prove mathematically that statement and verify if the circuit logic satisfy this condition.  The data enters the A and B cells through the first and the fourth prioritors.  Let N represents the new data and 'D' the old data.  When the data changes from 'D' to 'N' while the clock is at the infimum-state, the AD1=N^{¾ a#}, AQ2=D^{¾ a#}, BQ1=D and BD2=N.  The first condition is written mathematically in AOP as: if  N^{¾  a-}³D^{¾  a-} then N^{¾  a#¾a-}£D^¾a#¾a-.  The circuit satisfies this condition and it is proved in the costar relative priority theorem.