Illustrative and Complementary Information On
 The Algebra Of Priority (AOP )
By
Abu-Msameh, Ramadan K. 
April 16, 1999
Comments On Prioritors 
"The development of AOP was originated strictly for the purpose of describing and analyzing digital systems design"

This section "as is" from a paper on the applications of AOP in combinatorial circuits design. This section is not intended to give full details but rather shows some of the insights of AOP and its applications at the hardware level.

A z-radix digital system has z-distinct digits. Under AOP, each digit is represented in a digital system by a state, which has a definite boundary that defines its region. Any digital signal bounded by the state boundaries is said to be a valid signal that represents the digit defined by the state. The group of states for a digital system is called the digital system spectrum. In an electronic digital spectrum, digital signals are represented by electric energy, where we may represent a state by voltage, current, charge, frequency or phase shift, and digital circuits are implemented by semiconductors devices

Prioritors As “Digital Gates”

Gates in a digital system can be designed by using prioritors. In the practical world, a prioritor is a gate with two control signals: the supremum signal and the infimum signal. The supremum signal is used to close the gate and the infimum signal is used to open the gate. In a z-radix digital system we can design z! distinct-gates. Cascading prioritors is used to generate gates with more than two inputs. Figure-4 shows two prioritors used as gates. Part-A shows a prioritor with an input signal as in A1 and a control signal as in A2. The output signal is shown in A3. If we examine the output signal, we see that the gate passes the input signal at the infimum-state of the prioritor and blocks the input signal at the supremum-state. The infimum and supremum-states vary from one prioritor to another. Part-B shows the a* prioritor with an input signal as in B1 and a control signal as in B2. The output signal is shown in B3. If we examine the output signal, we see that the gate passes the input signal at the infimum-state of the a* prioritor which is the supremum-state of the a prioritor and blocks the input signal at the supremum-state of a* which is the infimum-state of the a prioritor. These signals are more cleared when they are specified and drawn on a state map. See Example-2.

Figure-5 shows prioritors used as gates in a data multiplexing circuit where a=Q7=4S1023, a*=QN=4S3201 and a=Q8=4S1032. The third prioritor is the star prioritor of a. The data selector selects the A-input at the supremum of a (a^{¾ L}=1) and selects the B-input at the infimum of a (a^{¾ V}=3). The S1 signal represents the A-input, S2 represents the B-input and S3 represents the control signal. The S4 shows the output on the first prioritor and S5 shows the output at the second prioritor. S6 shows the final output signal.

Prioritors can act as digital filters by passing certain signals and blocking other signals. They can be used in digital filtering applications. When we examine the priority assignment of any prioritor, we find that any digit filters out all the digits to its left and passes itself and all the digits to its right. For example, in 4S0123 the ‘0’ filters out all digits to its right and passes itself. The ‘1’ digits passes itself and the ‘0’ digit but filters out the ‘2’ and the ‘3’ digits. The ‘2’ digit passes itself and the ‘0’ and ’1’ digits but filters out the ‘3’ digit only. The ‘3’ digit passes itself and all other digits and it does not filter out any digit.

Figure-7 shows the Q3 and QM prioritors used as digital filters. In Part-A, the A1 is the input signal and the A2 is the control signal. At the 0-state of the control signal, the prioritor filters out all signals except for the ‘0’ signal. At the 1-state of the control signal, the prioritor filters out only the ‘3’ signal and passes the ‘0’, '1' and ‘2’. At the 2-state of the control signal, the prioritor filters out the ‘1’ and ‘3’ and passes the ‘0’ and '2' signal. At the 3-state of the control signal, the prioritor passes all signals and does not filter out any signal. The A4 signal is used to filter out the three signal at the 1-state and passes all other signals at the 3-state as shown in the A5 output signal. Part-B shows the QN prioritor. The B2 control signal is used to filter out the '0', '1' and '2' signals at the 3-state and filters out the '2' and '0' at the 1-state as shown in the B3 output signal. The B4 control signal is used to filter out the ‘0’ and ‘2’ at the 1-state and filters out '0', '1' and '2' signals at the 3-state as shown in the B5 output signal. Figure-4C shows prioritors as filters or wave converters. The S1 is the input wave and B1, B2 and B3 are the output waves. The third prioritor filters out the '2' and '3' signals from the input signal and converts it to a new wave form as shown in B3.

Figure-8 shows the circuit implementations of some of the theorems of AOP. The left circuit shows the left side in the theorem equation and the right circuit shows the right side in the theorem equation.

 

Figure-9 also shows the implementation of the following priority functions:

• R(A,B,C)= (AaC)a*(BaC^─yaA^─f)a*(A^─faBaC);

• T(A,B,C)= (AaB)a*(B^─faC)  

• S(A,B,C,D)=(A^{─ f}aBaC)a*(Aa*Ca*D);

• U(A,B,C)=(AaB)a*(Aa*C)a*(B^{─ f}aC).  

Simple Applications

Encoders and Decoders

Figure-22 (A) shows a 2-16 digit quaternary decoder. The input lines are decoded by unary orthogonal operators. Each unary orthogonal operator is given by Dxa^{¾ L}a^{¾ V} where 'x' is a digit indicated on the figure for each operator. The output is active at the infimum-state of the prioritor in use. For example if the input is '21' then the output of the prioritor labeled by '9' is equal to a^{¾ V} and all the other outputs are equal to a^{¾ L}.

 Figure-22 (B) shows a 16-2 digit quaternary encoder. All prioritors in the circuit must have an infimum-state of '0' (a^{¾ V}=0) like the QA, QC, QG, QI, QM, and QO. The circuit has two 3-input prioritors at the output stage. Each input at the output stage has one unary orthogonal operator. The unary orthogonal operators from top to bottom for each output are given by Da^{¾ L}01, Da^{¾ L}02 and Da^{¾ L}03 respectively. All inputs are active at the supremum-state of a and they must be set at a suitable state other than the active state. For example, a supremum-state signal at the B7 input drives the 4^th prioritor to a^{¾ L}.  This in returns switches the unary orthogonal operator from the '0' infimum-state to '1' , which makes A1=1 and in the same way A0 is set to '3' resulting in an output of  'A1A0=13' which is 7 in the decimal system.

Multiplexers and Demultiplexers

 Figure-23 (A) shows a 16-1 quaternary data multiplexer. The unary orthogonal operators and the 3-input prioritors obtain the decoding. The five 4-input prioritors at the output stage are the star of the input prioritors. They collect data to the Q-output. Each unary orthogonal operator is given by Dxa^{¾ L}a^{¾ V} where 'x' is a digit indicated on the figure for each operator. When the input is decoded, all of its lines are equal to a^{¾ V}. Thus at the input prioritor we will have (Dxa a^{¾ V} a a^{¾ V})=Dx which will appear at the Q-output. For example, let A1A0=32. The inputs at the prioritor #14 is (D14a a^{¾ V} a a^{¾ V})=D14. Now the output of all other input prioritors are at the supremum-state, therefore all inputs to the output prioritors are equal to the supremum-state (which is the infimum-state of the output prioritors) except for the output of prioritor #14 which is equal to D14. Thus at the last output prioritor we have (Dxa a^{¾ V} a a^{¾ V}a a^{¾ V})=Dx . Figure-23 (B) shows the 1-16 quaternary demultiplexer. It is obtained from the multiplexer circuit by shorting all input to a one-input and removing the prioritors 16, 17, 18, 19 and 20.

7-Segment LED Display Driver

Figure-24 shows a QCD (quaternary coded decimal) to 7-segment LED driver. The QCD inputs are decoded by the unary orthogonal operators and prioritors numbered '0'-'9' These decoded outputs are encoded by prioritor labeled 'a'-'g', and 'w'-'z' to activate the corresponding segments for each digit. The 'w'-'z' prioritors are used to simplify the interconnections. This specific circuit is best designed in the binary system and an interface circuit can be placed at its inputs to operate with none binary components. Because its prioritors actually use two signals and the remaining signals are unused, the hardware implemented for these unused signals also remains unused and will lead to a waste in hardware costs and production costs. Thus, we should call for mixed-radix systems. Such systems will take the best advantages of all radices in use.