The Electronic Implementation of Prioritors 

By

Abu-Msameh, R. K.

This section is from a paper on the electronic implementation of the operators of AOP. This section is not intended to give full details but rather shows that AOP was developed with an enormous concentration on circuit implementation of all of its operators.

The NVBP transistor is a bipolar four terminal semiconductor device, which MAY solve the implementation problem of MVL circuits at the hardware level and result in a successful MVTTL (Multi-Valued Transistor-Transistor Logic) family.

Prioritors are one of the basic building blocks of digital systems. In AOP, we presented the priority concept and used it to develop its operators and theorems. In this paper, we will use the same concept to develop the electronic implementation of prioritors.

AOP implements its prioritors at the hardware level based on three major concepts which are

1. Priority Concept

2. Power-Bus Concept

3. Switching Concepts of Junction-Devices

In AOP, we use the s-code to represent the priority-assignment of a prioritor. For example, the 4S1023 is the s-code for the priority-assignment of the Q7 prioritor. From the s-code, we know that a digit in the priority-assignment s-code always has a higher priority than any digit to its right and a less priority than any digit to its left. From this property we can electronically implement prioritors by assigning an NVBP transistor for each digit in the priority s-code. The NVBP transistors are organized in the implementation circuit in order from left-to-right as in the priority code. The first transistor in the circuit from left detects the first signal from left in the priority code. The second transistor detects the second digit from left in the priority code. The i^th transistor from left detects the i^th digit from left in the priority code. No transistor is provided to detect the last digit (First digit from right). To implement the priority principle by the hardware we use (z-i-1) NPN transistors for each NVBP transistor where 'i' is the transistor number counting from left to right and starting from one. The first NVBP transistor requires (z-2) NPN transistors, the second requires (z-3), the third (z-4) and so on. These NPN transistors are called the priority transistors. Each NPN transistor is connected in series between the power supply and the next NVBP transistors so that all the (z-i-1) NPN transistors have one common base. For example, in Figure-28 the NVBP transistors are organized from left to right as in the s-code (T16, T15, and T14). The first transistor (T16) from left always has the highest priority because it corresponds to the first digit from left in the priority code. The T16 transistor has two (4-1-1=2) NPN priority transistors which are T12 & T13. T13 is connected in series with the next NVBP transistor, which is T15.  T12 is connected in series with the next NVBP transistor, which is T14. These two transistors make the T16 has the highest priority. The T15 NVBP transistor is the second from left and has one (4-2-1=1) priority transistor (T11), which is connected in series with the T15 NVBP transistor. The T14 is the third from left and has zero (4-3-1=0) priority transistors, which means no priority transistors are needed. The total number of priority transistors is given by j(z)=½(z-1)(z-2). This number is zero for the binary system, one for the ternary system and three for the quaternary system.


11- The Electronic Implementation of Quaternary Prioritors

The quaternary system has twenty-four (4!=24) prioritors divided into four partitions where each partition has 6 prioritors.

Power-Bus Implementation (PBI)

Figure-28 shows the MVTTL 2-input quaternary prioritor for PBI systems. T11-T21 transistors form the input stage. T14-T19 are the decoding NVBP transistors and T11-T13 are the priority transistors. T2-T4 and T5-T7 are called the state transistors. T8-T10 are the inverting transistors. The inverting transistors are used to make all transistors of the NPN type and avoid using PNP transistors because electrons have higher mobilities than holes. If they are to be removed to minimize the number of elements in the circuit, then T5-T7 must be PNP transistors. The most important transistors in the circuit are the priority transistors.

How does the circuit operate? At each input, the possible input signals are 0,1,2 and 3. At each input, we need to detect the presence of A, B, and C signal. The 'D' signal is detected by knowing none of A, B and C signals were detected. For the A-input, T14-T16 detect the C, B and A respectively and for the B-input input, T17-T19 detect the C, B and A respectively. The collectors of the NVBP transistors of the B-input are connected to the collectors of the NVBP transistors of the A-input. This connections means 'A' or 'B' according to the definition of prioritors in AOP which simply states that the result of a prioritor is equal to 'A' if 'A' has the highest priority OR is equal to 'B' if B has the highest priority. Thus, the collector of T16 is connected to the collector of T19, the collector of T15 is connected to the collector of T18, and the collector of T14 is connected to the collector of T17. Therefore, the T16 and T19 detect the 'A' signal, the T15 and T18 detect the 'B' signal, the T14 and T17 detect the 'C' signal and the 'D' signal is detected by T2, T3 and T4. The state-transistors are A,B,C,D in the 4SABCD priority code where D=0^a, C=1^a, B=2^a, A=3^a.

Circuit Operation

(1) When T16 or T19 is ON, then its collector is pulled to ground and it turns OFF T12 and T13 which disable the results of T15, T18, T14 and T17. This action gives T16 and T19 the highest priority. The T4 and T10 are OFF and T7 is ON which result in a current flow in the A-State transistor, which corresponds to the A-state which is the supremum digit of the prioritor. (2) When T15 or T18 is ON, then its collector is pulled to ground and it turns OFF T11 which disabled the results of T14 and T17. This action gives T15 and T18 a higher priority than T14 and T17. The T3 and T9 are OFF and T6 is ON which result in a current flow in the B-State transistor which corresponds to the B-state which has priority higher than the 'C' and 'D' signals. (3) When T14 or T17 is ON, the T2 and T8 are OFF and T5 is ON which result in a current flow in the C-State transistor which corresponds to the C-state which has priority higher than the 'D' signal. (4) When all NVBP transistors T14-T19 are OFF, the T5-T7 are OFF and T2-T4 are ON which result in a current flow in the D-State transistor which corresponds to the D-state which has the least priority and is called the prioritor's infimum-digit. This also shows that T11, T12 and T13 set the priority of signals in a prioritor and that is why they are called the priority transistors. Table-6 shows the On/off State of each transistor in Figure-28. Table-2 shows the statistics of circuit elements needed to implement a prioritor in a z-radix system.  Less components can implement the same circuit in a different configuration.

For example, let a=4SABCD=4S2103. T16 and T19 will detect the 2-state, T15 and T18 will detect the 1-state, T14 and T17 will detect the 0-state, and T2, T3 and T4 will detect the 3-state. 'A' corresponds to the 2-state, 'B' corresponds to the 1-state, 'C' corresponds to the 0-state (short circuit) and 'D' corresponds to the 3-state.

Figure-29 shows the MVTTL 3-input quaternary prioritor for PBI systems. The circuit uses T20-T22 NVBP transistors for the third input. Note that all the collectors of the NVBP transistors of different inputs are connected together. The circuit function and specification is exactly as of Figure-28. The circuit can be expanded to an n-input terminal by adding three NVBP transistors for each input. The final number of NVBP transistors for an n-input prioritor is equal to n(z-1).

Simpler circuits can be obtained when applying other techniques by AOP.   All AOP digital circuits operate using a 5-volt regulated DC supply.  This voltage range is divided into four voltages to represent for digital-signals that can be used by the BTQ (Binary, Ternary and Quaternary) systems.